-- ### -------------------------------------------------------------- ###
-- #                                                                    #
-- # file       : mips_sts.vbe                                          #
-- # date       : august  1996                                          #
-- # version    : v0.0                                                  #
-- #                                                                    #
-- # origin     : this description has been developed by CAO-VLSI team  #
-- #              at MASI laboratory, University Pierre et Marie Curie  #
-- #              URA CNRS 818, Institut Blaise Pascal                  #
-- #              4 Place Jussieu 75252 Paris Cedex 05 - France         #
-- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
-- # Author      : fahim RAHIM_SARWARY                                  #
-- # Modif       : Arnaud Caron & Fahim Rahim                           #
-- # descr.      : Behavioural description for status and interrupts    #
-- #                                                                    #
-- # Modif 	: Tue Nov 19 12:50:15 WET 1996				#
-- # 		  suppression du scan path "maison..."                  #
-- ### -------------------------------------------------------------- ###

ENTITY mips_sts IS
  PORT( ck          : IN  BIT ;                      -- clock
	frz         : IN  BIT ;                      -- external freeze
	test        : IN  BIT ;                      -- test mode 
	opx_sign    : IN  BIT ;                      -- operdan's signs and 
	opy_sign    : IN  BIT ;                      -- result sign to
	alu_sign    : IN  BIT ;                      -- check the
	alu_nul     : IN  BIT ;                      -- alu result
	alu_c31     : IN  BIT ;
	alu_c30     : IN  BIT ;
	ctlalu	    : IN  BIT_VECTOR(5 DOWNTO 0);
	rs          : IN  BIT_VECTOR(4 DOWNTO 0);    -- register RS
	rd          : IN  BIT_VECTOR(4 DOWNTO 0);    -- register RD
	rdrt        : IN  BIT_VECTOR(4 DOWNTO 0);    -- register RD or RT
	mxrs_rdrt   : IN  BIT ;                      -- RD or RT  selection 
	wenable_in  : IN  BIT_VECTOR(10 DOWNTO 0) ;   -- wenable from sequencer
	ctlrw_in    : IN  BIT_VECTOR(4 DOWNTO 0) ;   -- MEM from SEQ
	ctlrw_out   : inout bit_vector(4 downto 1);
	adr0        : IN  BIT ;                      -- adr(0)
	adr1        : IN  BIT ;                      -- adr(1)
	adr31       : IN  BIT ;                      -- adr(31)

	intrqs      : IN  BIT_VECTOR(5 DOWNTO 0) ;   --  external interrupts
	intrqs_seq  : OUT BIT ;                      -- intr request to seq
	
        berr_s      : IN BIT;			     --  bus error

	scin        : IN  BIT ;                      -- seq_scout

	alu_test    : OUT BIT ;                      -- check the alu result

	redpnt      : OUT BIT_VECTOR(4 DOWNTO 0) ;   -- read register
	wrtpnt      : OUT BIT_VECTOR(4 DOWNTO 0) ;   -- write register 

	wenable_out : OUT BIT_VECTOR(6 DOWNTO 0) ;   -- wenable to datapath
	crsr_dpt     : IN BIT_VECTOR (15 DOWNTO 0);   -- registre satus and cause register from data-path
        crsr_out    : OUT BIT_VECTOR (15 DOWNTO 0);  -- register sataus and cause to data-path
 
	crsr_mx     : IN BIT ; 
	excp	    : in bit_vector(6 downto 0);
	rqs         : OUT BIT ;                      -- request to SEQ
        exq         : OUT BIT ;			     -- exp     to SEQ 
	rw          : OUT BIT ;                      -- ext read write
	rw_ctl      : OUT BIT_VECTOR(15 DOWNTO 0) ;  -- inout data ctl
	frz_ctl     : OUT BIT_VECTOR(15 DOWNTO 0) ;  -- out address ctl

	W           : OUT BIT_VECTOR(1 downto 0);
	scout       : OUT BIT ;                      -- scout ext

	vdd         : IN  BIT ;
	vss         : IN  BIT );

END mips_sts;

ARCHITECTURE behavioural of mips_sts is

  SIGNAL wrtpnt1     : BIT_VECTOR(4 downto 0) ;
  
  SIGNAL ctlrw_out_i : BIT_VECTOR(4 downto 0) ;



  -- signals to alu_test output

  SIGNAL slt_s                       : BIT;
  SIGNAL sgt_s			     : BIT;  
  SIGNAL sltu_s                      : BIT;
 
-- Modif suppression du signal sgtu_s  
--SIGNAL sgtu_s			     : BIT;


  -- exceptions

  --SIGNAL unkopc_s                   : BIT;
  --SIGNaL prvins_s                   : BIT;
  SIGNAL if_adderr_s                  : BIT;
  SIGNAL lh_adderr_s                  : BIT;
  SIGNAL lw_adderr_s                  : BIT;
  SIGNAL sgmterr_s		      : BIT;
  SIGNAL sw_adderr_s                  : BIT;
  SIGNAL sh_adderr_s		      : BIT;
  SIGNAL sw_adderr_en                 : BIT;
  SIGNAL sh_adderr_en                 : BIT;
  SIGNAL lw_adderr_en                 : BIT;
  SIGNAL lh_adderr_en                 : BIT;
  SIGNAL if_adderr_en                 : BIT;
  SIGNAL sgmterr_en 		      : BIT;
  SIGNAL dbe_en			      : BIT;
  SIGNAL ibe_en 		      : BIT;
  SIGNAL adel_x                       : BIT;
  SIGNAL ades_x                       : BIT;
  SIGNAL ibe_s			      : BIT;
  SIGNAL dbe_s			      : BIT;
  SIGNAL ri_x                         : BIT;
  SIGNAL cpu_x			      : BIT;
-- ajout pour l'ovf
  SIGNAL ovf_x			      : BIT;
--
  SIGNAL rireg_t                      : BIT;
  SIGNAL ibereg_t                     : BIT;
  SIGNAL dbereg_t                     : BIT;
  SIGNAL adelreg_t                    : BIT;
  SIGNAL adesreg_t		      : BIT;
  SIGNAL cpureg_t		      : BIT;
  SIGNAL intrqs_sysreg_t              : BIT;
  SIGNAL intrqs_brreg_t		      : BIT;
  SIGNAL rireg_x                      : BIT;
  SIGNAL ibereg_x                     : BIT;
  SIGNAL dbereg_x                     : BIT;
  SIGNAL adelreg_x                    : BIT;
  SIGNAL adesreg_x		      : BIT;
  SIGNAL cpureg_x		      : BIT;

-- ajout pour ovf
  SIGNAL ovfreg_x		      : BIT;
--

  SIGNAL intrqs_sysreg                : BIT;
  SIGNAL intrqs_brreg		      : BIT;
-- ajout ovfreg_t
  SIGNAL ovfreg_t		      : BIT;
--
  SIGNAL ibe_r			      : REG_BIT REGISTER;
  SIGNAL ri_r                         : REG_BIT REGISTER;
  SIGNAL dbe_r                        : REG_BIT REGISTER;
  SIGNAL adel_r                       : REG_BIT REGISTER;
  SIGNAL cpu_r			      : REG_BIT REGISTER;
  SIGNAL ades_r			      : REG_BIT REGISTER;
  SIGNAL intrqs_sys_r		      : REG_BIT REGISTER;
  SIGNAL intrqs_br_r		      : REG_BIT REGISTER;
-- ajout registre ovf
  SIGNAL ovf_r			      : REG_BIT REGISTER;

  --  wenable and mux for cause and status registers
  SIGNAL wen_cr  		      : BIT;	--cr wenable fro writing
  SIGNAL wen_erq		      : BIT;    --erq state

  --  cause register 

  SIGNAL cr_excod		     : BIT_VECTOR(3 downto 0);
  SIGNAL cr_ip			     : BIT_VECTOR(5 downto 0);
  SIGNAL cr_s			     : REG_VECTOR(15 downto 0) REGISTER;
  SIGNAL cr_out			     : BIT_VECTOR(15 downto 0) ;

  -- clock and wenable for cause and status register
   SIGNAL sr_ckd			     : BIT;
   SIGNAL sr_cke			     : BIT;
   --SIGNAL sr_ckr			     : BIT;
   SIGNAL cr_ckd			     : BIT;
   SIGNAL cr_cke 			     : BIT;
   SIGNAL wen_rfe                            : BIT; 
  -- status register
  
  SIGNAL sr_s			     : REG_VECTOR(15 downto 0) REGISTER;
  SIGNAL sr_out 		     : BIT_VECTOR(15  downto 0) ;
  SIGNAL wen_sr			     : BIT;
  SIGNAL sr_int			     : bit_vector(15 downto 0);
  SIGNAL cr_int			     : bit_vector(15 downto 0);

  -- interrupt and exception and reset request ...

  SIGNAL intrqs_s                   : BIT;
  SIGNAL excrqs_s                   : BIT;

  --  byte

  SIGNAL W_s                     : BIT_VECTOR( 0 to 1);
 

  -- Inout data and out address control

  SIGNAL  rw_ctl_n                      : BIT;
  SIGNAL  frz_ctl_n                     : BIT;
	

	constant e_sys	 : bit_vector (6 downto 0) := B"0010000";
	constant e_brk	 : bit_vector (6 downto 0) := B"0001000";
	constant e_ri     : bit_vector (6 downto 0):= B"0000010";
	constant e_cpu	 : bit_vector (6 downto 0) := B"0000001";
	constant e_nop	 : bit_vector (6 downto 0) := B"0000000";
	constant e_lw	 : bit_vector (6 downto 0) := B"0010001";
	constant e_lh	 : bit_vector (6 downto 0) := B"0010010";
	constant e_lb	 : bit_vector (6 downto 0) := B"0010100";
	constant e_sw	 : bit_vector (6 downto 0) := B"0011000";
	constant e_sh	 : bit_vector (6 downto 0) := B"0011100";
	constant e_sb	 : bit_vector (6 downto 0) := B"0011110";
	constant e_ifetch : bit_vector (6 downto 0):= B"0011111";
	constant e_ibe : bit_vector (6 downto 0):= B"0100000";
	constant e_dbe : bit_vector (6 downto 0):= B"1000000";
	constant e_clr : bit_vector (6 downto 0):= B"1010101";
	constant e_ovf : bit_vector (6 downto 0):= B"1111111";



  -- Description of the memory access modes

	-- Modif: Thu Nov  7 15:05:10 WET 1996
	-- Voir mips_seq ...
	-- constant m_wh    : bit_vector (4 downto 0) := B"01101" ;
	-- constant m_rh    : bit_vector (4 downto 0) := B"00100" ;
	constant m_no    : bit_vector (4 downto 0) := B"00001" ;
	constant m_fetch : bit_vector (4 downto 0) := B"10001" ;
	constant m_ww    : bit_vector (4 downto 0) := B"00000" ;
	constant m_wh    : bit_vector (4 downto 0) := B"00100" ;
	constant m_wb    : bit_vector (4 downto 0) := B"00010" ;
	constant m_rw    : bit_vector (4 downto 0) := B"01001" ;
--	ajout perso
	constant m_scan    : bit_vector (4 downto 0) := B"11000" ;
	

BEGIN

  -- alu_test

  sgt_s <= '1' WHEN (   ( opx_sign ='1' XOR opy_sign = '0' )
		    AND ( alu_sign = '0' )
		    AND ( alu_nul    = '0' ) )              ELSE
	   '1' WHEN ( opx_sign = '0' AND opy_sign = '1' ) ELSE
	   '0';

 -- Modif alu_c31 au lieu de sgtu_s   
  
  sltu_s <=  '1' when ( alu_c31 = '1' ) else
		'0';	

 
  slt_s <= NOT(alu_nul) AND NOT(sgt_s);

  

  --  alu_test output


  --    WITH ctlalu SELECT
  -- Modif erreur de constante 001100 au lieu de 001110 
  -- Modif syntaxe avec des else au lieu du with select 
    alu_test <= NOT sltu_s	WHEN (ctlalu = "001111") ELSE  
		NOT slt_s	WHEN (ctlalu = "001101") ELSE
		'1' ;



  --  register file addresses

  redpnt <= rs WHEN mxrs_rdrt = '1' ELSE
	    rdrt;




  wrtpnt1 <= rdrt     WHEN (wenable_in(10) & wenable_in(1 downto 0)          = B"100") ELSE
	     rd       WHEN (wenable_in(10) & wenable_in(1 downto 0)          = B"101")  ELSE
	     B"11111" WHEN (wenable_in(10) & wenable_in(1 downto 0) = B"110") ELSE
	     B"00000";

            
  wrtpnt <= wrtpnt1 ;

  --  wenable_out output

  wenable_out <= wenable_in( 10 DOWNTO 4 )
		 WHEN ( excrqs_s = '0' ) ELSE
		 "0000000";

  -- ctlrw_out output
  ctlrw_out_i <= ctlrw_in when(excrqs_s = '0' OR wenable_in(3) OR wenable_in(2))
          else "00001";
  ctlrw_out <= ctlrw_out_i(4 downto 1);

  ri_x         <= excp = e_ri ;                    --illegale codop
  -- Modif: Wed Nov  6 15:36:11 WET 1996
  cpu_x        <=( sr_s(1) AND (excp=e_cpu));  --coprossor unasable exeption

-- modif pour l'ovf
  ovf_x        <= ((alu_c30 XOR alu_c31) AND (excp=e_ovf));
--
  if_adderr_s  <= not (adr0 and adr1);	--ifetch or load word non algined address
  lh_adderr_s  <= not adr0; 		--load half non algined address
  lw_adderr_s  <= not(adr0 and adr1);  	--load word non aligned error
  sgmterr_s    <= (sr_s(1)) AND not(adr31);	--adress error segment
  sw_adderr_s  <= not(adr0 and adr1);		--store word address error
  sh_adderr_s  <= not(adr0);			--store half address error
  
  -- exceptions enable

  
  sw_adderr_en <= excp = e_sw;
  sh_adderr_en <= excp = e_sh;
  lw_adderr_en <= excp = e_lw;
  lh_adderr_en <= excp = e_lh;
  if_adderr_en <= excp = e_ifetch;
  sgmterr_en <= excp=e_sw OR excp=e_sh OR excp=e_sb OR excp=e_lb OR excp=e_lh OR excp=e_lw OR excp=e_ifetch ;
  dbe_en    <= excp = e_dbe ;
  ibe_en    <= excp = e_ibe OR excp = e_ifetch;


  adel_x <= (lw_adderr_s AND lw_adderr_en) 
         OR (lh_adderr_en AND lh_adderr_s) 
	 OR (if_adderr_s AND if_adderr_en)
	 OR (sgmterr_s AND sgmterr_en);
  ades_x <= (sw_adderr_s AND sw_adderr_en) 
         OR (sh_adderr_en AND sh_adderr_s) 
	 OR (sgmterr_en and sgmterr_s);

  ibe_s <= NOT(berr_s) AND ibe_en;
  dbe_s <= NOT(berr_s) AND dbe_en;
  
  -- exception signals for registers 

  rireg_x  <= ri_x OR ( ri_r AND not( wenable_in( 3 ) AND wenable_in(2 )) );
   ibereg_x  <= ibe_s OR ( ibe_r  AND not( wenable_in( 3 ) AND wenable_in(2 )) );
  dbereg_x  <= dbe_s OR ( dbe_r AND not( wenable_in( 3 ) AND wenable_in(2 )) );
  adelreg_x  <= adel_x OR ( adel_r AND  not( wenable_in( 3 ) AND wenable_in(2 )) );
  adesreg_x  <= ades_x OR ( ades_r AND not( wenable_in( 3 ) AND wenable_in(2 )) );
  cpureg_x  <= cpu_x OR ( cpu_r AND  not( wenable_in( 3 ) AND wenable_in(2 )) );
-- ajout pour ovf  
  ovfreg_x  <= ovf_x OR ( ovf_r AND  not( wenable_in( 3 ) AND wenable_in(2 )) );
--
  -- software interrupt for registers

  intrqs_sysreg <= (excp=e_sys) OR (intrqs_sys_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); 
  intrqs_brreg  <= (excp=e_brk)  OR (intrqs_br_r AND  not( wenable_in( 3 ) AND wenable_in(2 )) );


	intrqs_sysreg_t <= intrqs_sysreg when (frz = '0') else intrqs_sys_r;
	intrqs_brreg_t  <= intrqs_brreg  when (frz ='0') else intrqs_br_r;
	rireg_t 		<= ri_x when(frz ='0') else ri_r ;
	ibereg_t 		<= ibereg_x when(frz ='0') else ibe_r;
	dbereg_t 		<= dbereg_x when(frz ='0') else dbe_r;
	adesreg_t		<= adesreg_x when(frz = '0') else ades_r;
	adelreg_t 			<= adelreg_x when(frz ='0') else adel_r;
	cpureg_t		<= cpureg_x   when(frz = '0') else cpu_r;
-- ajout pour ovf	
	ovfreg_t		<= ovfreg_x   when(frz = '0') else ovf_r;
--
  --software interupt registers

  syscall : BLOCK(ck = '1' AND NOT ck'STABLE) 
  BEGIN
	intrqs_sys_r  <= GUARDED '0' when (excp = e_clr) else  intrqs_sysreg_t;
  END BLOCK;

  break : BLOCK(ck = '1' AND NOT ck'STABLE)
  BEGIN
	intrqs_br_r   <= GUARDED '0' when (excp = e_clr) else intrqs_brreg_t ;
  END BLOCK;

  -- exception's registers 



  ri : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    ri_r <= GUARDED '0' when (excp = e_clr) else rireg_t ;
  END BLOCK;


  ibe : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    ibe_r <= GUARDED '0' when (excp = e_clr) else ibereg_t ;
  END BLOCK;


  dbe : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    dbe_r <= GUARDED '0' when (excp = e_clr) else dbereg_t ;
  END BLOCK;

  ades : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    ades_r <= GUARDED '0' when (excp = e_clr) else adesreg_t ;
  END BLOCK;

  adel : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    adel_r <= GUARDED '0' when (excp = e_clr) else adelreg_t ;
  END BLOCK;

  cpu : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    cpu_r <= GUARDED '0' when (excp = e_clr) else cpureg_t ;
  END BLOCK;


  ovf : BLOCK( ck = '1' AND NOT ck'STABLE )
  BEGIN
    ovf_r <= GUARDED '0' when (excp = e_clr) else ovfreg_t ;
  END BLOCK;
  
-- exception's output in cause register
  cr_ip(0)   <= NOT(intrqs(0)) AND sr_s(0) AND sr_s(10);
  cr_ip(1)   <= NOT(intrqs(1)) AND sr_s(0) AND sr_s(11);
  cr_ip(2)   <= NOT(intrqs(2)) AND sr_s(0) AND sr_s(12);
  cr_ip(3)   <= NOT(intrqs(3)) AND sr_s(0) AND sr_s(13);
  cr_ip(4)   <= NOT(intrqs(4)) AND sr_s(0) AND sr_s(14);
  cr_ip(5)   <= NOT(intrqs(5)) AND sr_s(0) AND sr_s(15);


  cr_excod <= B"0000" when (cr_ip(0) or cr_ip(1) or cr_ip(2) or cr_ip(3)
  			 or cr_ip(4) or cr_ip(5)) and not(excrqs_s) else
              B"1010" when ri_r         = '1' else
              B"1011" when cpu_r        = '1' else
	      B"0100" when adel_r       = '1' else
	      B"0101" when ades_r       = '1' else
	      B"0110" when ibe_r        = '1' else
	      B"0111" when dbe_r        = '1' else
	      B"1000" when intrqs_sys_r = '1' else
	      B"1001" when intrqs_br_r  = '1' else	   
	-- ajout pour ovf
              B"1100" when ovf_r        = '1' else
	      
	--
	      B"1111";
 

  wen_erq <= (wenable_in(3) AND wenable_in(2) AND wenable_in(1) AND NOT(wenable_in(0)));
  wen_cr  <= (NOT(wenable_in(3)) AND (wenable_in(2)) AND NOT(wenable_in(1))) and not(excrqs_s) ;
  wen_sr  <= (wenable_in(3) AND NOT(wenable_in(2)) AND NOT(wenable_in(1))) and not(excrqs_s) ;
  wen_rfe <= (wenable_in (3) AND NOT(wenable_in(2)) AND wenable_in(1) AND wenable_in(0)) and not(excrqs_s);

 
  
  crsr_out <= sr_out when(crsr_mx ='1') ELSE
	      cr_out;
 
  
--***************************cause  register************************************************************--

       cr_ckd <=  wen_erq;
       cr_cke <=  wen_cr;
         
cr_int  <= cr_ip & cr_s(9 downto 6)& cr_excod & B"00" when (cr_ckd)  else 
	   cr_ip & crsr_dpt(9 downto 8) & B"00" & cr_s(5 downto 0) when (cr_cke) else
	   cr_s ;  
 cr_it : BLOCK(ck = '1' and not ck'stable )
	     BEGIN
                cr_s <= GUARDED cr_int;
	     END BLOCK cr_it;

  cr_out <= cr_s;

--****************************status register******************************--

        sr_ckd <=  wen_erq;
	sr_cke <=  wen_sr;
	sr_int <= sr_s(15 downto 6) & sr_s(3 downto 0) & B"00" when(sr_ckd) else 
	  	crsr_dpt when(sr_cke) else 
	  	sr_s(15 downto 4) & sr_s (5 downto 2)  when (wen_rfe )
        	else sr_s;

    	sr_rfe : BLOCK(ck = '1' and not ck'stable)
	BEGIN
		sr_s <= GUARDED sr_int; 
        END BLOCK sr_rfe;

	sr_out <=  sr_s ;

--**********************************************************************--
			
  --  rqs output 
  intrqs_s <=   NOT test AND (
      		   (cr_s(8) AND sr_s(8) AND sr_s(0)) 
		OR (cr_s(9) AND sr_s(9) AND sr_s(0)) 
		OR (NOT(intrqs(0)) AND sr_s(10) AND sr_s(0))
	        OR (NOT(intrqs(1)) AND sr_s(11) AND sr_s(0)) 
		OR (NOT(intrqs(2)) AND sr_s(12) AND sr_s(0))
		OR (NOT(intrqs(3)) AND sr_s(13) AND sr_s(0))
		OR (NOT(intrqs(4)) AND sr_s(14) AND sr_s(0))
		OR (NOT(intrqs(5)) AND sr_s(15) AND sr_s(0))
		OR intrqs_sys_r
		OR intrqs_br_r );
		-- Modif: syscall et break sont des interruptions !!!

  excrqs_s <=  NOT test AND (
	       ibe_r  OR ibe_s  OR
	       dbe_r  OR dbe_s  OR adel_r OR adel_x OR
	       ades_r OR ades_x OR ri_r   OR ri_x   OR  
	       cpu_r OR cpu_x OR ovf_r OR ovf_x );

  --rqs      <= (excp = e_clr) OR excrqs_s OR intrqs_s;
  rqs      <= excrqs_s OR intrqs_s;
  exq      <= excrqs_s;
  intrqs_seq   <= intrqs_s;

  -- rw, frz_ctl  and rw_ctl output

  rw_ctl_n   	<= ctlrw_out_i(0) OR frz OR ck OR test;
  frz_ctl_n 	<= frz OR test;

  rw_ctl(15)    <= NOT rw_ctl_n ;
  rw_ctl(14)    <= NOT rw_ctl_n ;
  rw_ctl(13)    <= NOT rw_ctl_n ;
  rw_ctl(12)    <= NOT rw_ctl_n ;
  rw_ctl(11)    <= NOT rw_ctl_n ;
  rw_ctl(10)    <= NOT rw_ctl_n ;
  rw_ctl(9)     <= NOT rw_ctl_n ;
  rw_ctl(8)     <= NOT rw_ctl_n ;
  rw_ctl(7)     <= NOT rw_ctl_n ;
  rw_ctl(6)     <= NOT rw_ctl_n ;
  rw_ctl(5)     <= NOT rw_ctl_n ;
  rw_ctl(4)     <= NOT rw_ctl_n ;
  rw_ctl(3)     <= NOT rw_ctl_n ;
  rw_ctl(2)     <= NOT rw_ctl_n ;
  rw_ctl(1)     <= NOT rw_ctl_n ;
  rw_ctl(0)     <= NOT rw_ctl_n ;

  frz_ctl(15)   <= NOT frz_ctl_n ;
  frz_ctl(14)   <= NOT frz_ctl_n ;
  frz_ctl(13)   <= NOT frz_ctl_n ;
  frz_ctl(12)   <= NOT frz_ctl_n ;
  frz_ctl(11)   <= NOT frz_ctl_n ;
  frz_ctl(10)   <= NOT frz_ctl_n ;
  frz_ctl(9)    <= NOT frz_ctl_n ;
  frz_ctl(8)    <= NOT frz_ctl_n ;
  frz_ctl(7)    <= NOT frz_ctl_n ;
  frz_ctl(6)    <= NOT frz_ctl_n ;
  frz_ctl(5)    <= NOT frz_ctl_n ;
  frz_ctl(4)    <= NOT frz_ctl_n ;
  frz_ctl(3)    <= NOT frz_ctl_n ;
   frz_ctl(2)    <= NOT frz_ctl_n ;
  frz_ctl(1)    <= NOT frz_ctl_n ;
  frz_ctl(0)    <= NOT frz_ctl_n ;

  -- byte
  rw   <= ctlrw_out_i(0);
  W_s  <= "11" WHEN (ctlrw_in = m_ww ) ELSE
	  "01" WHEN (ctlrw_in = m_wh ) ELSE
          "10" WHEN (ctlrw_in = m_wb ) ELSE
	  "00" ;

  W    <= W_s WHEN excrqs_s = '0' ELSE B"00";

  --  scout output ( non inverted )
  scout <= scin ;

END behavioural;




 






