                 BEGIN_MUX

                 MUX_MODEL        mx2_x2
                 MUX_SEL          cmd
                 MUX_INPUT_SEL    i1
                 MUX_INPUT_NSEL   i0
                 MUX_VDD          vdd
                 MUX_VSS          vss
                 MUX_OUTPUT       q

                 END_MUX

                 BEGIN_REG

                 REG_MODEL        sff1_x4
                 REG_CLK          ck
                 REG_INPUT        i
                 REG_VDD          vdd
                 REG_VSS          vss
                 REG_OUTPUT       q
                 REG_MUX          mx2_x2
                 REG_REG_MUX      sff2_x4

                 END_REG

                 BEGIN_REG_MUX

                 REG_MUX_MODEL        sff2_x4
                 REG_MUX_SEL          cmd
                 REG_MUX_INPUT_SEL    i1
                 REG_MUX_INPUT_NSEL   i0
                 REG_MUX_CLK          ck
                 REG_MUX_VDD          vdd
                 REG_MUX_VSS          vss
                 REG_MUX_OUTPUT       q
                 REG_MUX_MUX          mx2_x2
                 REG_MUX_REG          sff1_x4

                 END_REG_MUX

                 BEGIN_BUF

                 BUF_MODEL            buf_x2
                 BUF_INPUT            i
                 BUF_VDD              vdd
                 BUF_VSS              vss
                 BUF_OUTPUT           q

                 END_BUF
