# -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4

PortSystem              1.0
PortGroup               github 1.0

github.setup            verilator verilator 5.028 v
revision                0
categories              science electronics
license                 {LGPL-3 Artistic-2}
maintainers             {mcalhoun @MarcusCalhoun-Lopez} openmaintainer
description             Verilog compiler and simulator
long_description        Verilator is a {*}${description}.

checksums               rmd160  5d45fa63999302629f90488b340470fa6a619b73 \
                        sha256  45d7381a1e3f7bcb3bd7117950490c9d870c1ad7a75dc61abf6245c98b1fc4c1 \
                        size    32548221

compiler.cxx_standard   2014

use_autoconf            yes

installs_libs           no

depends_build-append    port:help2man

depends_lib-append      port:perl5.36
configure.perl          ${prefix}/bin/perl5.36

depends_build-append    port:flex
configure.env-append    LEX=${prefix}/bin/flex

depends_build-append    port:bison
configure.env-append    YACC=${prefix}/bin/bison

depends_lib-append      port:python311
configure.python        ${prefix}/bin/python3.11
configure.env-append    PYTHON3=${configure.python}

post-patch {
    foreach fl {verilator verilator_coverage verilator_includer} {
        reinplace "s|^#!/usr/bin/env perl\$|#!${configure.perl}|" ${worksrcpath}/bin/${fl}
    }
    foreach fl {verilator_ccache_report verilator_difftree verilator_gantt verilator_profcfunc} {
        reinplace "s|^#!/usr/bin/env python3\$|#!${configure.python}|" ${worksrcpath}/bin/${fl}
    }
}
